The invention relates to clock skew compensation.
Digital circuits (e.g., integrated circuits) include circuit elements that function according to a clock signal that is distributed throughout the circuit by a clock distribution network. In some cases, the topology of the clock distribution network is that of a tree. A clock tree has a clock source at the root of the tree and circuit elements at the leaves of the tree. The nodes of the clock tree are buffers (signal driving circuit elements) that drive some number of sinks. A sink can be a leaf circuit element or a buffer circuit element driving a sub-tree.
The structure of a clock tree can be described according to levels. Each node other than the root is connected to a “parent” node by a link in a graph representing the tree. The root of a tree is at level 0. The nodes directly connected to the root are at level 1. The nodes directly connected to nodes at level L are at level L+1. Thus, the level of a node is the number of links between the root and that node. The largest level is the depth D of the tree. Since a buffer has a limit to the number of sinks that it can drive (the “fanout” limit), an increase in the number of circuit elements driven by a clock tree, in some cases, calls for an increase in the depth of the clock tree.
The buffers in a clock tree (or other type of clock distribution network) introduce delay in the clock signal provided to a circuit element with respect to a reference clock signal (e.g., the signal at the root source node). Clock tree synthesis techniques are used to balance delay in different portions of a clock distribution network to meet setup and hold times for bistable multivibrator circuit elements such as flip-flops or latches. In some cases, this calls for reducing skew between clock signals at the inputs of circuit elements. For example, if the output of a first flip-flop is connected to the input of a second flip-flop, the rising edge of the clock supplied to the first flip-flop should be close enough to the rising edge of the clock supplied to the second-flip for the signal propagated between the flip-flops to meet the setup and hold time requirements of the second flip-flop. Balancing delays in a circuit can involve adding delay (e.g., with delay buffers) in logic paths of the circuit. In some cases, the clock distribution network is designed such that “useful skew” between clock inputs supplied to circuit elements is used to compensate for circuit delays to meet setup and hold times and improve overall system performance. Other techniques can be used to synchronize clock signals in a digital system, including using phase-locked loops to synchronize clock signals for different portions of a circuit.